In this post I demonstrate a solution to generalize the creation of class attributes for various write-count-limited scenarios, such as:

1. Class-level constant attributes (read-only)
2. Write-once attributes, i.e. can be written once and then become read-only
3. Object-level constant attributes (read-only)
4. Attributes which can be written a number of times up to a specified limit before becoming read-only

Generalizing

Upon inspection, it should become clear that

all of the above are actually cases of a general write-count limit in the range 0-N.

Specifically, for each case above, the write-count-limit is as follows:

1. write-count-limit = 0 (but the constant must be supplied at the…

Decorators in Python can quickly become a complicated matter when dealing with bound-methods (i.e. class-instance bound function calls). In some cases a basic decorator is required. In other cases, we would like to supply parameters to the decorator itself. We also would like to extend/modify decorator definitions and not have to implement the complexities each time. Lastly we would like to control execution before, during and after a wrapped method call and having each such phase be configurable.

After experimenting with a variety of approaches, I have come up with a generalized solution that enables highly configurable and extensible bound-method…

At some point in my Python OOP journey, I came across dataclasses. I vaguely recall this coming about when generating seemingly repetitive boilerplate code for a class that did little more than containing a rather lengthy data-record. Hoping there was a better way to do this lead me to discover dataclasses which were introduced in Python 3.7 (via PEP 557).

In a nutshell, the dataclasses make developing and maintaining data-centric classes simpler.

In this post I wanted to share some discoveries as they relate to more interesting class implementations and also how such “interesting” dataclasses can be easily leveraged by…

Decades of logic gates and wires

The year is 2021, and the bulk of silicon and FPGA designers are still describing designs at the register-transfer-level (RTL) abstraction. Despite two major evolutions in the Verilog design language, the design subset only gained constructs to better generate and organize wires. This is not to say that there aren’t examples of designs being done at higher-levels such as C++ but this is far from ubiquitous (for reasons I will discuss).

How should hardware description languages (HDLs) evolve to raise the aggregate abstraction of design-intent? And more important, why should they?

In this article I will share my thoughts on…

Introduction

In this article I describe how this seemingly provocative concept is actually a template for up-leveling development to attain high-velocity and efficient use of people-time.

Although this concept can be applied to any phase of development, I focus on the front-end phases which define architectures and the direction for development because this is the phase which has the most impact on downstream teams. I will show that although this is a powerful paradigm, the requisite capabilities are not trivial and need to be grown and developed.

Not really Failure

If Thomas Edison “failed” 10,000 times so he can “succeed” once in taming incandescence…

This is the final part of my series of articles about delegation for technology leaders. I would love to write more on this topic, but to do so, I need to learn more through observation and experience.

In this installment, we look at the temporal properties of delegation, followed by listing possible outcomes resulting from systematic delegation including the busting of our final myth and close out with a more formalized definition of delegation.

Temporal Response

The effectiveness of delegation in relation to time can be a function of many dependent variables. The benefit (or lack thereof) of delegation moves in lockstep…

FIFOs (First-In, First-Out) are point-to-point elastic storage elements that are very commonly used in embedded systems to pass data across an asynchronous interface in a very efficient manner. In this context, asynchronous simply means that the two ends of the FIFO are behaving independently save for some initial signaling to initiate a transfer.

A typical question that silicon or FPGA architects are often faced with is how big should they make a FIFO? …

Continuing with the theme of the big opportunities started in Part 4 where we discussed the potential benefits of an open-source RISC ISA, in this installment, we look at how embedded security may benefit from open-source approaches

Embedded security is no longer the realm of specialized chips or markets (such as banking or military). These days, any general purpose microcontroller or application processor needs to provide security supporting not just application-level security (such as required by communications protocols), but also secure boot, secure key storage and beyond.

Security in general, is a never-ending process.

It is a process because it…